위치 : 싱가폴
처우: 경력에 따른 연봉협의. 하우징, 항공료, 비자편의, 첫달 정착비 제공

문의 및 이력서제출: steve@scout.co.kr

CAD Engineer
 
Responsibilities :
 
• Develop and support automation programs (SKILL, OCEAN, Tcl) for front-end and back-end CAD flows (Spice and Verilog simulations, schematic capture,

layout, etc)
• Develop, test, and integrate physical verification rule decks for DRC, LVS and LPE within Assura and Calibre
• Update existing Pcells to be Virtuoso XL compatible
• Provide expert-level problem solving support for day to day front-end and back-end issues and PDK maintenance
• Implement analog customer layout and digital P & R layout with layout team
• Develop and implement a productive design methodology by collaborating with design team
• Support of Linux/Unix workstation based servers and clients, setting up OS, updates, disk/file management and user management

Requirements :
• PhD in Engineering  with at least 5 years' experience providing support for full-custom front-end and back-end CAD flow in a semiconductor design

group or equivalent
• Proficient in Linux/Unix environment
• Expert level experience with creating custom analog physical layouts within the Cadence Virtuoso environment, and digital P & R physical layout

within Cadence and Synopsys environment
• Experience with setting up shared and mirrored vaults, projects, as well as users accounts
• Experience with Verilog RTL, Mixed Signal Co-simulator, and other CAD tools
• Exposure to advanced CMOS process technologies
• Conversant in several of the following areas:
o Programming in SKILL, OCIEAN, Tcl, Perl
o Verilog, Assura and Calibre based DRC/VLS/LPE flow development
o Circuit simulation